In arrays of analog memory cells, such as in Flash memory devices, memory cells may suffer from interference from other memory cells in the array. This interference may introduce read errors and therefore degrade the storage reliability of the memory. Various techniques for interference estimation and cancellation in analog memory cell arrays are known in the art.
For example, PCT International Publication WO 2007/132457, whose disclosure is incorporated herein by reference, describes a method for operating a memory device. The method includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells of the memory device. After storing the encoded data, second analog values are read from the respective memory cells of the memory device in which the encoded data were stored. At least some of the second analog values differ from the respective first analog values. A distortion that is present in the second analog values is estimated. Error correction metrics are computed with respect to the second analog values responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data. Other example interference cancellation methods are described in PCT International Publication WO 2007/132453, whose disclosure is incorporated herein by reference.
In some known techniques, compensation for interference is carried out during programming of the memory cells. For example, U.S. Pat. No. 7,885,119, whose disclosure is incorporated herein by reference, describes techniques that compensate for electric field coupling in a programming process that takes into account the programmed state of an adjacent memory cell. To determine whether compensation is needed, the process may include sensing information about the programmed state of the adjacent memory cell, for example on an adjacent bit line or other location.
As another example, PCT International Publication WO 2009/038961, whose disclosure is incorporated herein by reference, describes a programming process for a given memory cell, which verifies the amount of programming after each programming pulse. The standard verify level for the programming cell is dependent on the target state. The verify level is further offset lower dependent on the amount of perturbation from neighboring cells, determinable by their target states.